Method of manufacturing semiconductor device

ABSTRACT

An SOI layer is thinned without a thermal oxidation process. An SOI substrate ( 10 ) is immersed in an etching bath filled with an NH 3 —H 2 O 2 —H 2 O solution to be isotropically etched. This produces a 100-nm thick SOI layer ( 3 ) with no crystal defect.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of manufacturing asemiconductor device, especially, a method of manufacturing asemiconductor device formed on an SOI substrate.

[0003] 2. Description of the Background Art

[0004] Semiconductor devices (SOI device) formed on an SOI (Silicon OnInsulator) substrate have advantages such as reduced junctioncapacitance and improved element isolation breakdown voltage, oversemiconductor devices (bulk device) formed on a bulk substrate.

[0005]FIG. 5 is a cross-sectional view of an SOI substrate 10. The SOIsubstrate 10 has a structure with a buried oxide film 2 and a singlecrystalline silicon layer (hereinafter referred to as “SOI layer”) 3stacked on the main surface of a silicon substrate 1. In FIG. 5, theburied oxide film 2 is approximately 370 nm thick, and the SOI layer 3is approximately 200 nm thick.

[0006] At the time of forming the substrate, the thickness of the SOIlayer 3 of the SOI substrate 10 is approximately 200 nm as shown in FIG.5. However, in the manufacture of semiconductor devices, the SOI layer 3has to be reduced in thickness according to specs of desiredsemiconductor devices, which is called a thinning process of the SOIlayer 3.

[0007] As shown in FIG. 6, the SOI layer 3 is thinned to a moderatethickness in a semiconductor element forming region (active region) ARof the main surface of the SOI substrate 10.

[0008] When the thickness of the SOI layer required for the manufactureof semiconductor devices is 100 nm, for example, the SOI layer 3 of theSOI substrate 10 has to be reduced by about 100 nm since its originalthickness is approximately 200 nm.

[0009] Conventionally, techniques for thermally oxidizing the SOI layer3 have been adopted to make the SOI layer 3 thinner. More specifically,the SOI substrate 10 is heated to about 1000° C. and exposed to anoxygen atmosphere for thermal oxidation so that a 220-nm thick thermaloxide film 4 is formed on the SOI layer 3 as shown in FIG. 7. Thisconsumes about 100 nm of silicon which forms the SOI layer 3, therebyreducing the SOI layer 3 to approximately 100 nm.

[0010] After the removal of the thermal oxide film 4 with a hydrofluoricacid solution, the SOI layer 3 of the SOI substrate 10 has a thicknessof about 100 nm as shown in FIG. 8.

[0011] The problem here is surplus silicon (injected siliconinterstitial during oxidation), i.e., a phenomena that interstitialsilicon atoms occurring in the interface between silicon and a siliconoxide film during thermal oxidation of the SOI layer 3 form crystaldefects DF in the SOI layer 3 as shown in FIG. 8. When semiconductordevices are formed in the SOI layer 3 with the crystal defects DF,abnormal leakage current will occur during operation of the devices.

[0012]FIG. 9 schematically shows an example that CMOSs (ComplementaryMOSs) are formed in the thinned SOI layer 3. In FIG. 9, the SOI layer 3is electrically divided into an NMOS region with a plurality of N-typeMOSFETs (N-MOSFETs) 15 and a PMOS region with a plurality of P-typeMOSFETs (P-MOSFETs) 25 by an element isolation film 5 formed of aninsulating film such as a silicon oxide film.

[0013] The N-MOSFET 15 has a P type impurity region 14 with P-typeimpurities doped into the SOI layer 3; a gate oxide film 11 formed onthe P-type impurity region 14; a gate electrode 12 formed on the gateoxide film 11; and source/drain regions 13 with N-type impuritiesrelatively highly doped therein which are formed in the SOI layer 3 tosandwich the P-type impurity region 14 from both sides.

[0014] The P-MOSFET 25 has an N-type impurity region 24 with N-typeimpurities doped into the SOI layer 3; a gate oxide film 21 formed onthe N-type impurity region 24; a gate electrode 22 formed on the gateoxide film 21; and source and drain regions with P-type impuritiesrelatively highly doped therein which are formed in the SOI layer 3 tosandwich the N-type impurity region 24 from both sides.

[0015] As shown in FIG. 9, MOSFETs including the crystal defects DF areformed in proportion to a crystal defect density in the formation of aplurality of MOSFETs in the SOI layer 3 having the crystal defects DF.This results in characteristic anomalies and malfunction.

[0016]FIGS. 8 and 9 only schematically show the crystal defects DF inthe SOI layer 3, and actual crystal defects are more complicated.Further, it is difficult to detect the as-is status of crystal defectsafter the thermal oxidation for thinning the SOI layer, so that thepresence of crystal defects is confirmed by manifesting the crystaldefects by means of selective etching such as Secco etching.

[0017] The Secco etching refers to an etching using an etchant, socalled “Secco” or an etching using as an etchant an aqueous solution ofa mixture of 0.15-mol potassium dichromate (K₂Cr₂O₇) and 48% ofhydrofluoric acid (HF) in the ratio of 1:2. This is to manifest crystaldefects by using a characteristic that the etching rate in a portionwith crystal defects is higher than that in a portion with no crystaldefect.

[0018] In this fashion, the conventional thinning method of the SOIlayer included the thermal oxidation process of the SOI layer, so thatit had a problem of causing crystal defects in the SOI layer due to thethermal oxidation.

SUMMARY OF THE INVENTION

[0019] A first aspect of the present invention is directed to a methodof manufacturing a semiconductor device comprising the steps of:preparing an SOI substrate; isotropically etching an SOI layer of theSOI substrate to a predetermined thickness with an NH₃—H₂O₂—H₂Osolution; and forming semiconductor devices on the thinned SOI layer.

[0020] According to a second aspect of the present invention, in themanufacturing method of the first aspect, the ratio of components NH₃and H₂O₂ in the NH₃—H₂O₂—H₂O solution stands at 1:1.

[0021] According to a third aspect of the present invention, in themanufacturing method of the second aspect, the ratio of components inthe NH₃—H₂O₂—H₂O stands at 1:1:5 and a temperature of the solutionranges from 50° C. to less than 100° C.

[0022] According to a fourth aspect of the present invention, in themanufacturing method of the second aspect, the ratio of components inthe NH₃—H₂O₂—H₂O stands at 1:1:1 and a temperature of the solutionranges from 50° C. to less than 100° C.

[0023] A fifth aspect of the present invention is directed to a methodof manufacturing a semiconductor device comprising the steps of:preparing an SOI substrate; isotropically etching an SOI layer of theSOI substrate to a predetermined thickness by means of down flowetching, wherein plasma is produced by excitation of a predeterminedetching gas by high frequency or microwaves and radicals which arechemically active atoms or molecules included in the plasma aretransported to the SOI substrate along a flow of the etching gas to beused as etching species; and forming semiconductor devices on thethinned SOI layer.

[0024] According to a sixth aspect of the present invention, in themanufacturing method of the fifth aspect, the etching gas is either ofmixed gas of CF₄ and O₂, mixed gas of NF₃ and O₂, Cl₂ gas, mixed gas ofCl₂ and NF₃, or NF₃ gas.

[0025] In the method of manufacturing a semiconductor device of thefirst aspect, silicon atoms are removed progressively from the surfaceof the SOI layer since the SOI layer is isotropically etched to apredetermined thickness with the NH₃—H₂O₂—H₂O solution. Thus, surplussilicon is not produced in the SOI layer, which prevents occurrence ofcrystal defects in the SOI layer due to surplus silicon. This results inprevention of occurrence of characteristic anomalies or malfunction dueto crystal defects when semiconductor devices are formed in the thinnedSOI layer.

[0026] In the method of manufacturing a semiconductor device of thesecond aspect, the ratio of components NH₃ and H₂O₂ in the NH₃—H₂O₂—H₂Osolution stands at 1:1. This prevents surface roughness of the SOIlayer.

[0027] In the method of manufacturing a semiconductor device of thethird aspect, the ratio of components in the NH₃—H₂O₂—H₂O solutionstands at 1:1:5 and the temperature of the solution ranges from 50° C.to less than 100° C. This avoids too low etching rate of the SOI layerand allows controllable etching of the SOI layer.

[0028] In the method of manufacturing a semiconductor device of thefourth aspect, the ratio of components in the NH₃—H₂O₂—H₂O solutionstands at 1:1:1 and the temperature of the solution ranges from 50° C.to less than 100° C. This increases the etching rate of the SOI layer ascompared to the case where the rate stands at 1:1:5, and also allowscontrollable etching of the SOI layer.

[0029] In the method of manufacturing a semiconductor device of thefifth aspect, silicon atoms are removed progressively from the surfaceof the SOI layer since the SOI layer is isotropically etched to apredetermined thickness by the down flow etching. Thus, surplus siliconis not produced in the SOI layer, which prevents occurrence of crystaldefects in the SOI layer due to surplus silicon. This results inprevention of occurrence of characteristic anomalies or malfunction dueto crystal defects when semiconductor devices are formed in the thinnedSOI layer. Further the down flow etching uses radicals as etchingspecies, transporting those radicals to the SOI substrate along a flowof etching gas. This prevents the SOI substrate from being exposed tocharged particles in plasma, thereby preventing occurrence of crystaldefects in the surface of the SOI layer due to ion bombardment.

[0030] The method of manufacturing a semiconductor device of the sixthaspect allows effective etching of the SOI layer.

[0031] Thus, an objective of the present invention is to achieve amethod for thinning an SOI layer without using a thermal oxidationprocess.

[0032] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIGS. 1 through 3 are diagrammatic illustrations of a method ofmanufacturing a semiconductor device according to a first preferredembodiment of the present invention.

[0034]FIG. 4 is a diagrammatic illustration of a method of manufacturinga semiconductor device according to a second preferred embodiment of thepresent invention.

[0035]FIGS. 5 and 7 through 9 are diagrammatic illustrations of aconventional method of manufacturing a semiconductor device.

[0036]FIG. 6 is a diagrammatic illustration of an active region of asemiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] 1. First Preferred Embodiment

[0038] Referring to FIGS. 1 through 3, we will now describe a method ofmanufacturing a semiconductor device according to a first preferredembodiment of the present invention.

[0039]FIG. 1 is a cross-sectional view of an SOI substrate 10. The SOIsubstrate 10 has a structure with a buried oxide film 2 and a singlecrystalline silicon layer (hereinafter referred to as “SOI layer”)stacked on the main surface of a silicon substrate 1. In FIG. 1, theburied oxide film 2 is approximately 370 nm thick, and the SOI layer 3is approximately 200 nm thick.

[0040] When the thickness of the SOI layer required for the manufactureof semiconductor devices is 100 nm, for example, the SOI layer 3 has tobe reduced by about 100 nm. This requires that the SOI substrate 10 beisotropically etched by so-called wet etching using as an etchant anaqueous solution of a mixture of aqua ammonia and hydrogen peroxidewater, namely, NH₃—H₂O₂—H₂O solution.

[0041] More specifically, the SOI substrate 10 is immersed in an etchingbath filled with the NH₃—H₂O₂—H₂O solution to be isotropically etched.At this time, a dip method is adopted to circulate the NH₃—H₂O₂—H₂Osolution in the bath. After the etching processing, the SOI substrate iscleaned with running water.

[0042] Here we set the ratio of components in the NH₃—H₂O₂—H₂O solutionat 1:1:5 and the temperature of the solution at 50° C. or over. Thissolution is produced, for example, from aqua ammonia containing 30 wt %of ammonia and hydrogen peroxide water containing 30 wt % of hydrogenperoxide.

[0043]FIG. 2 shows the SOI substrate 10 with the 100-nm thick SOI layer3 thinned by the isotropic etching. The SOI layer 3 in FIG. 2 has nocrystal defect. This is because the isotropic etching using theNH₃—H₂O₂—H₂O solution as an etchant removes silicon atoms progressivelyfrom the surface of the SOI layer 3, instead of consuming silicon atomsby thermal oxidization of the SOI layer 3 as in the conventionaltechniques. This method does not produce surplus silicon in the SOIlayer 3, thereby preventing occurrence of crystal defects in the SOIlayer 3 due to surplus silicon.

[0044] When the NH₃—H₂O₂—H₂O solution having the aforementioned ratio isused as an etchant, the etching rate R (Å/min) of silicon, i.e., the SOIlayer, can be expressed by: $\begin{matrix}{R = {1.49 \times 10^{18}{\exp \left( \frac{- 1.21}{kT} \right)}}} & (1)\end{matrix}$

[0045] In Equation (1), k is Boltzman's constant and T is the absolutetemperature of the solution. For the solution temperature of 50° C., theetching rate is approximately 0.2 Å/min. When the etching rate may beless than 0.2 Å/min, it is needless to say that etching may be performedat a solution temperature of less than 50° C.

[0046] To shorten time for the etching processing, the etching rateneeds to be increased. There are two techniques for this: a techniquefor increasing the solution temperature; and a technique for varying theratio of components in the solution.

[0047] According to the technique for increasing the solutiontemperature, when the solution temperature is set at 80° C., the etchingrate is approximately 8 Å/min from Equation (1). Thus, etching the100-nm (i.e., 1000 Å) SOI layer requires the processing time of about125 minutes. This 125-minute etching processing may be performed at atime, but may be divided and not performed at one time.

[0048] According to the technique for varying the ratio of components inthe solution, the etching rate is increased by increasing the ratios ofNH₃ and H₂O₂ to H₂O while maintaining the NH₃—H₂O₂ ratio of 1:1. Thatis, the ratio of components in the NH₃—H₂O₂—H₂O solution is set at 1:1:1and the temperature of the solution is set at 80° C. The etching rate inthis case is approximately 40 Å/min, so etching the 100-nm SOI layerrequires the processing time of about 25 minutes.

[0049] It is also possible to increase the ratio of NH₃ to H₂O₂ largerthan 1:1 to increase the etching rate, but this may cause surfaceroughness of the SOI layer. To prevent this, the ratio between H₂O₂ andNH₃ should preferably be 1:1. In other words, surface roughness of theSOI layer can be effectively prevented by increasing the ratio of H₂O₂to NH₃. If the surface roughness of the SOI layer especially turns intoproblems, the ratio of NH₃ to H₂O₂ may be set to be less than 1 afterunderstanding of reduction in etching rate.

[0050] At either of the ratios of components in the NH₃—H₂O₂—H₂Osolution: 1:1:5 and 1:1:1, the etching rate can be increased by furtherincreasing the solution temperature. The increase in the solutiontemperature, however, accelerates evaporation of H₂O and increasesdeterioration of the solution components with time, causing difficultyin controlling the amount of etching of the SOI layer. Thus, thesolution temperature should preferably be 50° C. or over and at leastless than 100° C.

[0051]FIG. 3 schematically shows an example that CMOSs are formed in thethinned SOI layer 3. In FIG. 3, the SOI layer 3 is electrically dividedinto an NMOS region with a plurality of N-MOSFETs 15 and a PMOS regionwith a plurality of P-MOSFETs 25 by an element isolation film 5 formedof an insulating film such as a silicon oxide film.

[0052] The N-MOSFET 15 has a P-type impurity region 14 with P-typeimpurities doped in the SOI layer 3; a gate oxide film 11 formed on theP-type impurity region 14; a gate electrode 12 formed on the gate oxidefilm 11; source/drain regions 13 with N-type impurities relativelyhighly doped therein which are formed in the SOI layer 3 to sandwich theP-type impurity region 14 from both sides.

[0053] The P-MOSFET 25 has an N-type impurity region 24 with N-typeimpurities doped in the SOI layer 3; a gate oxide film 21 formed on theN-type impurity region 24; a gate electrode 22 formed on the gate oxidefilm 21; and source/drain regions 23 with P-type impurities relativelyhighly doped therein which are formed in the SOI layer 3 to sandwich theN-type impurity region 24 from both sides.

[0054] Since the SOI layer 3 has no crystal defect as shown in FIG. 3,no characteristic anomaly or malfunction occurs due to crystal defects.

[0055] Characteristic Effect

[0056] According to the aforementioned first preferred embodiment of thepresent invention, the SOI layer is thinned by removing silicon atomsprogressively from the surface by isotropic etching using theNH₃—H₂O₂—H₂O solution as an etchant. Thus, surplus silicon is notproduced in the SOI layer, which prevents the occurrence of crystaldefects in the SOI layer due to surplus silicon. This results inprevention of characteristic anomalies or malfunction due to crystaldefects when semiconductor devices are formed in the thinned SOI layer.

[0057] Further, the above thinning process of the SOI layer is performedat low temperatures from 50° C. to less than 100° C., at which thermaloxidation hardly proceeds. Thus, the SOI substrate is not heated to1000° C. or over unlike the conventional SOI substrate. This avoids theproblem of causing crystal defects by thermal stress of the SOIsubstrate.

[0058] Furthermore, the NH₃—H₂O₂—H₂O solution is usually used to cleansilicon substrates, which especially has the effect of removingparticles. Accordingly, particles stuck to the SOI substrate can also beremoved.

[0059] Modification

[0060] While the isotropic etching uses the NH₃—H₂O₂—H₂O solution as anetchant to thin the SOI layer in the first preferred embodiment, theetchant may be a sodium hydroxide (NaOH) solution or a potassiumhydroxide (KOH) solution.

[0061] The sodium hydroxide solution and the potassium hydroxidesolution are characterized by easy handling and no need of heatingbecause of its high etching rate even at room temperature.

[0062] For instance, the etching rate of the sodium hydroxide solutionwith a weight concentration of about 15% is approximately 100 nm/min ata temperature of 60° C.; and the etching rate of the potassium hydroxidesolution with a weight concentration of about 20% is approximately 100nm/min at a temperature of 60° C.

[0063] 2. Second Preferred Embodiment

[0064] In the method of manufacturing a semiconductor device accordingto the first preferred embodiment of the present invention, the SOIlayer is isotropically etched by wet etching in the thinning process,but the SOI layer may be thinned by dry etching. In a method ofmanufacturing a semiconductor device according to a second preferredembodiment of the present invention, the SOI layer is thinned bychemical dry etching using plasma, especially, by down flow etching.

[0065] The chemical dry etching with plasma uses, as etching species,excited-state atoms or molecules (hereinafter referred to as “radicals”)which are chemically active and produced in plasma excited by highfrequency or microwaves.

[0066]FIG. 4 is a layout sketch of a down flow etcher 100 which performsdown flow etching. As shown in FIG. 4, the down flow etcher 100 mainlycomprises an etching chamber 31 for accommodating the SOI substrate 10to be etched; a plasma production chamber 32 connected to the etchingchamber 31; a microwave generator 33 for plasma production; awave-guiding channel 35 for guiding microwaves (e.g., 2.45 GHz)outputted from the microwave generator 33 to an electrode plate 34 inthe vicinity of the plasma production chamber 32. The microwavegenerator 33 may be substituted by a high-frequency generator to exciteplasma by high frequency.

[0067] Next, we will describe operation of the down flow etcher 100.First, the SOI substrate 10 to be etched is placed on a mounting stage39 in the etching chamber 31 with the SOI layer 3 on the top. Then, avacuum system (not shown) evacuates air from the etching chamber 31 andthe plasma production chamber 32 through an exhaust pipe 37 to produce avacuum.

[0068] After that, a valve 36 of a gas feeding pipe 38 connected to theplasma production chamber 32 is opened to introduce a given amount ofetching gas. The etching gas is, for example, mixed gas of CF₄ and O₂,mixed gas of NF₃ and O₂, Cl₂ gas, mixed gas of Cl₂ and NF₃, or NF₃ gas.

[0069] The etching gas introduced into the plasma production chamber 32is excited by microwaves applied to the electrode plate 34, whichproduces plasma PZ. Although charged particles (ions and electrons)forming the plasma PZ have a short life, the lifetime of radicals RD islong. Thus, the radicals RD are transported to the etching chamber 31along a flow of etching gas and then chemically react with the surfaceof the SOI substrate 10, i.e., silicon atoms of the SOI layer 3 in theetching chamber. Thus, the SOI layer 3 is removed progressively from thesurface. The etching rate of the mixed gas of CF₄ and O₂, for example,ranges from 150 to 200 nm/min.

[0070] The down flow etching uses the radicals RD as etching species sothat the SOI substrate 10 is not exposed to charged particles in theplasma PZ. This prevents occurrence of crystal defects in the surface ofthe SOI layer 3 due to ion bombardment.

[0071] Characteristic Effect

[0072] According to the aforementioned second preferred embodiment ofthe present invention, the SOI layer is thinned by removing siliconatoms progressively from the surface by down flow etching. Thus, surplussilicon is not produced in the SOI layer, which prevents the occurrenceof crystal defects in the SOI layer due to surplus silicon. This resultsin prevention of characteristic anomalies or malfunction due to crystaldefects when semiconductor devices are formed in the thinned SOI layer.

[0073] Further, the down flow etching prevents the SOI substrate frombeing exposed to charged particles in plasma. Thus, no crystal defect isproduced in the surface of the SOI layer due to ion bombardment.

[0074] Furthermore, in the down flow etching, the SOI substrate is notheated to such temperatures that thermal oxidation proceeds, i.e. 1000°C. or over, unlike the conventional SOI substrate. This avoids theproblem of causing crystal defects by thermal stress of the SOIsubstrate.

[0075] While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

We claim:
 1. A method of manufacturing a semiconductor device comprisingthe steps of: preparing an SOI substrate; isotropically etching an SOIlayer of said SOI substrate to a predetermined thickness with anNH₃—H₂O₂—H₂O solution; and forming semiconductor devices in said thinnedSOI layer.
 2. The manufacturing method according to claim 1, wherein theratio of components NH₃ and H₂O₂ in said NH₃—H₂O₂—H₂O solution stands at1:1.
 3. The manufacturing method according to claim 2, wherein the ratioof components in said NH₃—H₂O₂—H₂O stands at 1:1:5 and a temperature ofsaid solution ranges from 50° C. to less than 100° C.
 4. Themanufacturing method according to claim 2, wherein the ratio ofcomponents in said NH₃—H₂O₂—H₂O stands at 1:1:1 and a temperature ofsaid solution ranges from 50° C. to less than 100° C.
 5. A method ofmanufacturing a semiconductor device comprising the steps of: preparingan SOI substrate; isotropically etching an SOI layer of said SOIsubstrate to a predetermined thickness by means of down flow etching,wherein plasma is produced by excitation of a predetermined etching gasby high frequency or microwaves and radicals which are chemically activeatoms or molecules included in said plasma are transported to said SOIsubstrate along a flow of said etching gas to be used as etchingspecies; and forming semiconductor devices on said thinned SOI layer. 6.The manufacturing method according to claim 5, wherein said etching gasis either of mixed gas of CF₄ and O₂, mixed gas of NF₃ and O₂, Cl₂ gas,mixed gas of Cl₂ and NF₃, or NF₃ gas.